A conventional semiconductor memory device of this type is shown in FIG. 1. Its configuration will now be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an example of construction of a memory cell sense amplifier of the prior art DRAM.
In this DRAM, a plurality of pairs of bit lines (only two of them, BL1a and BL1b being shown) and a plurality of word lines (only two of them, WL1 and WL2 being shown) are provided, and at their intersections, memory cells (only two of them, 10-1 and 10-2 being shown) of a one-transistor type are connected. Each of the memory cells 10-1 and 10-2 comprises an enhancement-type n-channel MOSFET (NMOS transistor) 11 and a capacitor 12. The gates of the NMOS transistors 11 are connected to the word lines WL1 and WL2 and the drains and sources of the NMOS transistors 11 are connected between the bit lines BL1a and BL1b and the storage nodes Nm, and the capacitors 12 are connected between the storage nodes Nm and a node of a fixed potential V.sub.0 (e.g., Vcc/2).
First and second sense amplifiers 21 and 22 are connected across each pair of the bit lines BL1a and BL1b. The first and the second sense amplifiers 21 and 22 are activated by a potential on the sense amplifier common nodes Nsn and Nsp. The first sense amplifier 21 is comprised of a flip-flop having two NMOS transistors 21a and 21b. The second sense amplifier 22 is comprised of a flip-flop having two enhancement-type p-channel MOSFETs (PMOS transistors) 22a and 22b.
Connected between the respective pairs of bit lines BL1a and BL1b are bit line equalizing sections 23. Each equalizing section 23 is activated by an equalizing signal EQ (e.g. of the power supply voltage Vcc), which sets the bit lines BL1a and BL1b to a potential on a power supply node Nv (e.g., Vcc/2), and comprises two NMOS transistor 23a and 23b connected in series between the bit lines BL1a and BL1b and are turned on and off by the equalizing signal EQ.
Connected between the sense amplifier common nodes Nsn and Nsp, and the power supply node Nv are common node precharging sections 24 which are turned on by the equalizing signal EQ to precharge the common nodes Nsn and Nsp. The precharging section 24 has NMOS transistors 24a and 24b turned on and off by the equalizing signal EQ, and the NMOS transistor 24a is connected between the power supply node Nv and the common node Nsn, while the NMOS transistor 24b is connected between the power supply node Nv and the common node Nsp.
Connected to the power supply node Nv is a reference potential generator 25. This reference potential generator 25 generates a reference potential, e.g., of 1/2 of the power supply potential Vcc supplied from the outside of the DRAM, and supplies it to the power supply node Nv.
The reading operation and the writing operation of FIG. 1 will now be described with reference to FIG. 2.
First, the reading operation is described.
During the stand-by period (mode), the equalizing signal EQ is High (=Vcc), the NMOS transistors 23a and 23b are turned on, and the bit lines BL1a and BL1b are charged to Vcc/2, a potential equal to that on the power supply node Nv. In accordance with the equalizing signal EQ, the NMOS transistors 24a and 24b in the precharging sections 24 are turned on, and the sense amplifier common nodes Nsn and Nsp are also charged to Vcc/2, a potential equal to the potential on the power supply node Nv. The word lines WL1 and WL2 are at the ground potential Vss, so the NMOS transistors 11 in the memory cells 10-1 and 10-2 are off, and the storage nodes Nm hold the information. Assume for the purpose of the following explanation, that, during read operation period, when for instance the word line WL1 is selected and charged to Vcc+Vth (Vth represents the threshold voltage of the NMOS transistor), and the data "1" (=Vcc) on the storage node Nm in the memory cell 10-1 is read.
In the operation of reading from the memory cell 10-1, if the word line WL1 is charged to Vcc+Vth after the equalizing signal EQ is changed to the Low (=Vss) level, the NMOS transistor 11 in the memory cell 10-1 is turned on, and bit line BL1a and the storage node Nm are connected to each other, and the bit line BL1a is raised to Vcc/2+.alpha., and the bit line BL1b is maintained at Vcc/2.
By discharging the sense amplifier common node Nsn from the Vcc/2 level to the Vss level, the first sense amplifier 21 is activated. At the same time, the sense amplifier common node Nsp is charged from the Vcc/2 level to the Vcc level, to activate the second sense amplifier 22. The potential difference .alpha. between the bit lines BL1a and BL1b is thereby amplified. As a result, the line BL1b is discharged to the Vss level, and the bit line BL1a is charged to the Vcc level. As a result, at the time of termination of the sense amplifier operation, the bit line BL1a will be at the Vcc level, and the bit line BL1b will be at the Vss level, and the storage node Nm is again charged to the Vcc level through the NMOS transistor 11 in the memory cell 10-1.
The memory information read onto the bit lines BL1a and BL1b are passed through a transfer gate selected by a column decoder, not shown, to a data bus, and the information on the data bus is transferred through an output buffer to the outside, and the reading is thus completed.
In the subsequent stand-by period, the word line WL1 is discharged to the Vss level, and the NMOS transistor 11 in the memory cell 10-1 is turned off, and the storage node Nm is made in the holding state. The equalizing signal EQ is thereafter raised to the High level (=Vcc) and the NMOS transistors 23a, 23b, 24a and 24b are turned on and the bit lines BL1a and BL1b and the sense amplifier common nodes Nsn and Nsp are again charged to Vcc/2 to be ready for next cycle of operation.
During writing operation, in contrast to the reading operation shown in FIG. 2, external information, not shown, is transferred through an input buffer to the data bus, and the information on the data bus is transferred through the transfer gate selected by the column decoder to the bit lines BL1a and BL1b, the information on the bit line BL1a is written through the NMOS transistor 11 in the memory cell 10-1 onto the storage node Nm. Through this process, the external information is stored in the memory cell 10-1.
In this type of conventional DRAM, when using the DRAM, if the user wanted to clear all the information that has been previously stored (erase the information in the memory cells to the physical "0"), it was necessary to write the physical "0" bit by bit or to wait until the information in the memory cells vary to the physical "0" due to the natural discharge of the memory cells themselves. Writing the physical "0" bit by bit however is time consuming, and the control procedure is complicated. Waiting until the natural discharge also takes time, and retards future accessing of the memory until the discharge is completed.